Device and method for timing error management

ABSTRACT

A device having timing error management capabilities and a method for timing error management. The device includes a first input node adapted to receive input data; a first latch, a second latch and a comparator, rising a first multiplexer and a second multiplexer; wherein the second multiplexer is adapted to provide input data to the second latch from the first input mode during a first operational mode of the device and to provide a first latch output signal to the second latch during a second operational mode; wherein the comparator is adapted to compare, during a first clock phase, between the first latch output signal and between a second latch output signal and in response to the comparison selectively generate an error signal.

FIELD OF THE INVENTION

The present invention relates to devices that have timing errormanagement capabilities and to methods for timing error management.

BACKGROUND OF THE INVENTION

Mobile devices or devices, such as but not limited to personal dataappliances, cellular phones, radios, pagers, lap top computers, and thelike are required to operate for relatively long periods before beingrecharged. These mobile devices usually include one or more processorsas well as multiple memory modules and other peripheral devices.

The power consumption of a transistor-based device is highly influencedby leakage currents that flow through the transistor. The leakagecurrent is responsive to various parameters including the thresholdvoltage (Vt) of the transistor, the temperature of the transistor,supply voltage and the like. Transistors that have higher Vt arerelatively slower but have lower leakage currents while transistors thathave lower Vt are relatively faster but have higher leakage current.

In order to reduce the power consumption of mobile devices various powerconsumption control techniques were suggested. A first technique usesdomino circuits that include both high threshold voltage transistors andlow threshold voltage transistors. U.S. patent application number2004/0008056 of Kursun et al., which is incorporated herein byreference, discloses a domino circuit that is configured such as toreduce power consumption, for example by limiting the energy consumedduring power switching.

Yet another technique is based upon creating a stack effect thatinvolves shutting down multiple transistors of the same type that areserially connected to each other. U.S. Pat. No. 6,169,419 of De et al.,which is incorporated herein by reference, discloses a method andapparatus for reducing standby leakage current using a transistor stackeffect. De describes a logic that has both a pull up path and a pulldown path.

A further technique includes reducing the clock frequency of the mobiledevice. Yet a further technique is known as dynamic voltage scaling(DVS) or alternatively is known as dynamic voltage and frequency scaling(DVFS) and includes altering the voltage that is supplied to a processoras well as altering the frequency of a clock signal that is provided tothe processor in response to the computational load demands (alsoreferred to as throughput) of the processor. Higher voltage levels areassociated with higher operating frequencies and higher computationalload but are also associated with higher energy consumption.

Very aggressive DVS techniques are illustrated in “DVS for On-Chip BusDesigns Based On Timing Error Correction”, H. Kaul, D. Sylvester, D.Blaauw, T. Mudge and T. Austin, Proceedings of the Design, Automationand Test in Europe Conference and Exhibition (DATE'05) and “Razor: A LowPower Pipeline Based on Circuit-Level Timing Speculation”, D. Ernst, N.S. Kim, S. Das, S. Pant, R. Rao, T. Pham, C. Ziesler, D. Blaauw, T.Austin, K. Flautner and T. Mudge, 36^(TH) Annual International Symposiumon Microarchitecture (MICRO-36), December 2003. These aggressive DVStechnique are based upon the assumption that power savings can beincreased if the supplied voltage level (and clock signal frequency)will be responsive to error occurring in a circuit and not be responsiveto the voltage level (and clock signal frequency) that should besupplied to a theoretical circuit that is characterized by worst-casescenarios of environment and process variations. In a nutshell thesupplied voltage level (and clock frequency) are lowered until error arebeing detected. It is noted that the error rate dramatically increaseswhen the voltage level decreases below a certain voltage level.

FIG. 1 illustrates a prior art flip-flop 10 as illustrated in the firstarticle while FIG. 2 illustrates a prior art flip-flop 11 as illustratedin the second article. Prior art flip-flop 11 differs from prior artflip-flop 10 by including a meta-stable detector 50 and an additionallogical gate 60 that is connected to the output of the meta-stabledetector 50 and to comparator 28 that compares the output of first latch41 and shadow latch 43.

Flip-flop 10 includes input inverter 12, output inverter 24, first latch41, second latch 42, shadow latch 43 and comparator 28. The first andsecond latches 41 and 42 are serially connected to each other. Theoutputs of first latch 41 and shadow latch 43 are connected to inputs ofcomparator 28. The output of comparator 28 generates an error indicationError. First latch 41 includes first transfer gate 14 that is seriallyconnected to first inverter 16. The output of first inverter 16 isconnected to a first input of first multiplexer 26. Another input offirst multiplexer 26 is connected to an output of shadow latch 43. Firstmultiplexer 26 is controlled by Error and its output is connected to theinput of first latch 16. Second latch 42 includes second transfer gate18 followed by a pair of inversely connected second and third inverters20 and 22. The output of second latch 42 is connected to an input ofoutput latch 24. The output of second transfer gate 18 is connected toan input of comparator 28.

The input of first transfer gate 14 and of shadow transfer gate 30 areconnected to an output of input inverter 12. First transfer gate 14 isclocked by a clock signal (Clk) and shadow transfer gate 30 is clockedby a delayed clock signal (Clk_delayed). Second transfer gate 18 ofsecond latch 42 is clocked by an inverted clock signal (Clk_inv).Accordingly, first latch 41 latches data at the rising edge of Clk,second latch 42 latches data at the falling edge of Clk and shadow latch43 latches data at a certain delay (usually slightly before the fallingedge of Clk) from the rising edge of Clk.

Prior art flip-flop 11 further includes a meta-stable detector 50 thatis connected to the output of second latch 42 and its output isconnected to a first input of or gate 60. The other input of OR gate 60is connected to the output of comparator 28. The output of OR gate 60provided error signal Error.

Meta-stable detector 50 includes fourth till sixth inverters 52, 54 and56 and an AND logic gate 58. The output of second latch 42 is connectedto the inputs of fourth and sixth inverters 52 and 56. The output ofsixth inverter 56 is connected to an input of AND logic gate 58. Thefifth inverter 54 is connected between the AND logic gate 58 and thefourth inverter 52.

Both flip-flops 10 and 11 perform error detection by comparing betweendata stored at shadow latch 43 and data stored at first latch 41,wherein the comparison occurs at the falling edge (after 50% of theclock cycle) of the clock cycle. Accordingly, only a small portion ofthe clock cycle is allocated for error detection propagation.

In addition, error recovery takes another clock cycle and data stored atshadow latch 43 is sent to first latch 41 via first multiplexer 26.

FIG. 3 is a timing diagram of a clock signal and an effective clocksignal that illustrates loss of one clock cycle due to each errorrecovery session. Curve 290 (referred to as Clk 290) eight clock cycles(CYCLE1-CYCLE8) of clock signal Clk 290. Curve 300 (referred to aseffective clock signal) illustrates the clock cycles that are used fordata processing. At CYCLE3 and CYCLE 7 a clock recovery processoccurred, thus these cycle were not used for data processing andaccordingly were omitted from curve 300.

There is a growing need to find effective devices and methods for timingerror management.

SUMMARY OF THE PRESENT INVENTION

A device and a method for timing error management, as described in theaccompanying claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be understood and appreciated more fully fromthe following detailed description taken in conjunction with thedrawings in which:

FIG. 1 illustrates a prior art flip-flop;

FIG. 2 illustrates a prior art flip-flop;

FIG. 3 is a timing diagram of a clock signal and an effective clocksignal that illustrates loss of one clock cycle due to each errorrecovery session;

FIG. 4 illustrates a device, according to an embodiment of theinvention;

FIG. 5 illustrates a power management module, according to an embodimentof the invention;

FIG. 6 illustrates a flip-flop, according to an embodiment of theinvention;

FIG. 7 is a timing diagram of clock signals, according to an embodimentof the invention;

FIG. 8 is a flow chart of a method for timing error management,according to various embodiments of the invention; and

FIG. 9 is a flow chart of a method for power management, according tovarious embodiments of the invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

A device (70) having timing error management capabilities, the device(70) includes a first input node (91) adapted to receive input data; afirst latch (141), a second latch (142) and a comparator (129); a firstmultiplexer (72) and a second multiplexer (74); wherein the secondmultiplexer (74) is adapted to provide input data to the second latch(142) from the first input mode (91) during a first operational mode ofthe device (70) and to provide a first latch output signal to the secondlatch (142) during a second operational mode; wherein the comparator(129) is adapted to compare, during a first clock phase, between thefirst latch output signal and between a second latch output signal andin response to the comparison selectively generate an error signal.

A method (200) for timing error management, the method (200) includes:determining (210) an operational mode of a device; providing (230),during a first operational mode, a data input to a second latch and to afirst latch; wherein the first latch is opened during a second phase ofa clock cycle and the second latch is opened during a first phase of theclock cycle; detecting (250) a timing error during the first phase ofthe clock cycle if a value latched in the second latch differs from theinput data; and providing (240), during a second operational mode, anoutput signal of the first latch to the second latch.

The inventors noticed that in prior art flip-flops (such as flip-flops10 and 11) an error is detected at the falling edge of the clock signaland if new input data is received at the shadow latch 43 during thefirst half (high clock phase) of the clock cycle. If, on the other hand,input data changes during the second half (during low clock phase) ofthe clock cycle then the flip-flop is deemed to function properly,without the occurrence of timing violations.

In a first operational mode (such as a normal operational mode) in whichinput data is expected to be stable data during high clock phase, theinput data can be directly sent to the second latch (that is open duringthe low clock phase). The first latch can operate as a shadow latch,thus the number of latches within the flip-flop decreases by around 33%.In addition, once an error is detected the second latch already storesthe right data, thus there is no need to waste additional time for errorrecovery that includes transferring the right data from the shadow latchto the second latch.

In a second operational mode the timing of signals dramatically changesin relation to the timing of signals during normal mode. These timingdifferences are caused by propagation of signals through scan circuits(and not normal circuits) that are usually very short. Accordingly,there is a high probability that data will change during the high clockphase input. In this operational mode or any other operational mode thatis characterized by a high probability of data change during first phaseof clock cycle the input data propagates through the first latch andthen through the second latch.

FIG. 4 is a schematic illustration of a device 70 according to anembodiment of the invention. Device 70 may include multiple frequencyregions as well as a single frequency region. Each frequency region caninclude its own error detection and error correction circuits.Typically, multiple flip-flops such as flip-flops 110 having errordetection capabilities are used to generate error signals. These errorsignals can be provided to a power management module 80 that in responsecan adjust the voltage/frequency supplied to a frequency region. Thepower management module 80, matches between the voltage level and clockfrequency provided to the frequency region by applying matchingtechniques known in the art. It is noted that the frequency can bematched d to the voltage but the voltage can also be matched to thefrequency.

Device 70 includes various units such as but not limited togeneral-purpose processor 72, I/O module 74, memory unit 76, peripheral78, and digital signal processor (DSP) 81. These units are linked toeach other by various lines and buses and receive clock signals andpower supply from one or more sources, illustrated by power managementmodule 80. It is noted that device 70 can include other units, that someof these unit are optional and that device 70 can include multiple unitsof the same kind. The power management module 80 can include one or morepower management modules, one or more clock signal sources, one or morevoltage supply sources and the like. Conveniently, a pair of clocksignal source and a voltage source are connected to a synchronizer thatsynchronizes the increment (or decrement) of the voltage level and theclock signal frequency, such as to prevent a case in which the voltagesupplied to one or more units is too low to support the clock frequencyof the clock signal. This matching is usually useful when altering theoperational mode of the integrated circuit and applying Dynamic Voltageand Frequency Scaling techniques. It is noted that the alteration of thevoltage/frequency can involve applying error rate based techniques aswell as DVFS techniques. For example, an initial voltage/frequency levelcan be set by applying DVFS and can be altered by applying error basedtechniques. Device 70 can set the voltage/frequency in response to errorindication as well as to its operational mode and load indications fromvarious components of device 70.

Typically, device 70 includes multiple busses and lines and the variousunits of device 70 can be connected to the same bus, but this is notnecessarily so. For convenience of explanation FIG. 4 illustrates asystem bus 89 that is shared by units 72, 74, 76, 78 and 81.

It is noted that device 70 can have various configurations and that theunits illustrated in FIG. 4 represent only a single exemplaryconfiguration of a device that applies the power reduction technique.Typically, device 70 can be a mobile device such as a cellular phone, amusic player, a video player, a personal data accessory, and the like.

Modern cores such as processor 72 and DSP 81 can include millions oftransistors. Device 70, or at least some of its units (such as but notlimited to processor 72 and DSP 81) can operate in various operationalmodes, including low power modes such as but not limited to an idle(also being referred to a shut down or standby) mode. During an idlemode it is desired to reduce the power consumption of a device,especially in view of the low computational load imposed on said deviceduring the idle mode.

It is noted that the power management module 80 can tolerate certainerror rates before increasing the voltage/frequency. The tolerated errorrates can be determined in view of a timing penalty imposed due to theerrors and in view of power consumption factors.

It is noted that flip-flops 100 can also located within components thatdiffer from processor 72 and DSP 81.

FIG. 5 illustrates power management module 80 according to an embodimentof the invention.

Power management module 80 includes a controller 250 adapted todetermine the voltage/frequency supplied to one or more frequencyregions of device 70, in response to load indications and/or errorindications.

Controller 250 is connected to voltage supply unit 270 and to clocksignal provider 82. For simplicity of explanation clock source 200 andload indications provided from various components to controller 250 arenot shown.

The clock signal generator 82 receives a clock signal Clock0 from clocksignal source 200 and also receives an error indicator from OR gate 230and provide a clock signal that may substantially equal clock0 or may bedelayed in relation to clock0. Clock signal generator 82 can generatemultiple different delayed clock signals (Clock1-ClockJ) and then selectbetween the clock0-ClockJ. A new clock signal is selected whenever anerror is detected. The inventors used ten delay units that provided tendelayed clock signals, spaced apart by a delay of about 10% of the clockcycle. It is noted that other delay periods can be provided. By delayingthe clock cycle once an error occurs many timing errors can beprevented, as the effective propagation period is slightly expanded.Conveniently, an increment of 10% of the effective propagation period(during error recovery) reduces the error rate by a ration of about1:10.

Conveniently, Clock1-ClockJ are delayed by delay periods Delay1, Delay2,. . . , DelayJ, wherein the Delay1<Delay2< . . . <DelayJ.

Error signals (Error) provided from flip-flops 100 arrive to OR gate230. If a single error occurs the OR gate 230 outputs a generate errordetection signal that is provided to counter 220 that in turn alters theselect signal it provides to multiplexer 240. Multiplexer 240 receives anon-delayed clock signal (Clock0) from clock signal source 200 and inaddition receives J delayed clock signals (J being a positive integer)Clock1-ClockJ from delay units 201-209 and selects one clock signal tobe provided to device 70. Counter 220 rolls over when it reaches to(J+1) so that when the (J+1)′Th error occurs the non-delayed clocksignal is provided to device 70. Accordingly, a single clock cycle isrequired to amend (J+1) errors.

It is noted that other clock signal generators can be provided,including clock signal generators that have a variable delay unit, butthis is not necessarily so.

FIG. 6 illustrates a flip-flop 110 according to an embodiment of theinvention.

Flip-flop 110 includes a first input node 91 adapted to receive inputdata (Din) during a first operational mode of device (70) and a secondinput node 92 adapted to receive another input data (such as scan modeinput data Sin) during a second operational mode of device 70. Firstinput node 91 is connected to a first input of first multiplexer 72 andto a first input of second multiplexer 74. A second input of firstmultiplexer 72 is connected to second input node 92. A second input ofsecond multiplexer 74 is connected to an output of output inverter 140.

An output of first multiplexer 72 is connected to first latch 141 thatincludes a first transfer gate 114 followed by a pair of inverselyconnected inverters 116 and 126. The output of inverter 116 is connectedto output inverter 140. The output of output inverter 140 is alsoconnected to a first input of comparator 128. The output of comparator129 is connected to AND gate 130 that also receives Clock at its otherinput, so that to ignore comparisons made by comparator 128 during thelow clock phase. Thus, changes in the input data occurring during thelow clock phase (and result in a difference between the input data tothe data latched in first latch 141) do not generate an error signal.

An output of second multiplexer 74 is connected to second latch 142 thatincludes a second transfer gate 118 that is followed by a pair ofinversely connected inverters 120 and 122. The output of inverter 120 isconnected to inverter 124. The output of second transfer gate 118 isalso connected to a second input of comparator 128.

First transfer gate 114 is clocked by a clock signal (Clock) and secondtransfer gate 118 is clocked by an inverted clock signal (Clock_inv).Accordingly, first latch 141 latches data at the rising edge of Clockand second latch 142 latches data at the falling edge of Clock.

Conveniently, when device 70 operates at a first operational mode (suchas a normal operational mode) the data signal (Din) is provided to firstand second latch. Din passes directly to second latch 142 that is openduring the low clock phase of Clock. Changes of input data Din duringthe high clock phase of a certain clock cycle are detected by thecomparison between the data latched in second latch 142 (reflecting thevalue of data signal during a previous clock cycle) and the data that isoutputted from output inverter 140. These differences are generatedimmediately (once the input data changes) thus allowing longer errorsignal propagation periods.

During a second operational mode, such as during scan mode, the inputdata passes through the first latch and just then passes through thesecond latch. In this operational mode the operational frequency can berelatively low and timing violations can be less relevant.

FIG. 7 is a timing diagram illustrating clock signals according to anembodiment of the invention.

Curve 292 illustrates a clock signal Clock0 generated by clock signalsource 200. It is assumed that at CYCLE1 of Clock0 the clock signalgenerator 80 selects to provide Clock0 to flip-flop 100. In other wordsduring CYCLE1 and CYCLE2 Clock equals Clock0.

Curve 300 illustrates clock signal Clock. At CYCLE2 an error wasdetected as in response the power management module 80 selects toprovide Clock1 during CYCLE3-CYCLE6. Clock1 is delayed by D1 311 thusduring CYCLE 3 an effective clock cycle of (CYCLE0+D1) is provided. AtCYCLE6 another error is detected and power management module 80 selectedClock2. Clock2 is delayed by delay period D2 312 in relation to Clock0.During CYCLE7 and CYCLE8 clock signal Clock2 is provided to flip-flop100.

FIG. 8 is a flow chart of method 200 for power management according toan embodiment of the invention.

Method 200 starts by stage 210 of determining an operational mode of adevice. The operational modes can include a normal operational mode anda scan operational mode. It is noted that various low power modes can bereferred to as examples of the first operational mode.

If a first operational mode is selected then stage 210 is followed bystage 230, else stage 210 is followed by stage 240.

Stage 230 includes providing, during a first operational mode, a datainput to a second latch and to a first latch. The first latch is openedduring a first clock phase and the second latch is opened during asecond clock phase. These latches can be opened by different clocks. Thefirst clock phase can differ from the second clock phase, can at leastpartially overlap the second clock phase and the like. Conveniently thefirst clock phase is the high clock phase while the second clock phaseis the low clock phase but this is not necessarily so. Typicallytransfer gate control when the latches are open (conducting,transparent) and when they are closed (non-conducting, blocking).

Stage 230 is followed by stage 250 of detecting a timing error duringthe first clock phase if a value latched in the second latch differsfrom the input data.

Stage 240 includes providing, during a second operational mode, anoutput signal of the first latch to the second latch. This secondoperational mode can be a scan mode but this is not necessarily so. Thesecond operational mode is characterized by input data changes that canoccur during the first clock phase, without being regarded as resultingfrom timing errors.

Stage 250 and optionally stage 240 are followed by stage 280 ofdetermining operational parameters (such as voltage level and/or clocksignal frequency) in response to at least one error indication and/orload consumed by (or expected to be consumed by) at least one componentof the device.

Conveniently, stage 250 includes detecting errors during the high clockphase while ignoring differences between the input data and the secondlatch output signal during a second clock phase.

Conveniently, stage 250 includes immediately detecting a timing error.Referring to the flip-flop illustrated in FIG. 6, once input datachanges (during the first clock phase) the comparison between the inputdata and the second latch output signal immediately indicates that anerror occurs. This is contrary to the error detection of flip-flops 11and 10 in which the comparison occurs after the first clock phase ends.

Conveniently, stage 250 includes performing a logical OR operations onmultiple error signals provided from pairs of first and second latched.

Conveniently, stage 250 is followed by stage 260 of delaying the clocksignal provided to the first latch and to the second latch in responseto a reception of a timing error indication.

Conveniently, stage 260 includes delaying the clock signal by about 10%of the clock cycle.

FIG. 9 is a flow chart of method 300 for power management according toan embodiment of the invention.

Method 300 starts by stage 310 of providing a clock signal and a supplyvoltage to at least one component of a device. Stage 310 is followed bystage 330 of detecting 330 a timing error.

Conveniently, stage 330 of detecting includes detecting a timing erroronly during a first operational mode of the device.

Stage 330 is followed by stage 350 of delaying, by a fraction of a clockcycle, and in response to the detected timing error, a clock signalprovided to at least one of the components. The fraction can besubstantially equal to 10% but this is not necessarily so.

Stage 350 is followed by stage 370 of determining a clock signalfrequency and/or a level of the supply voltage in response to at leastone detected timing error.

Conveniently, stage 350 of delaying includes generating multiple delayedversions of a clock signal and selecting between the delayed versions.

According to an embodiment of the invention method 300 also includesstage 315 of determining an operational mode of a device. If a firstoperational mode is selected then stage 315 is followed by stage 316,else it is followed by stage 318. Stage 316 includes providing, during afirst operational mode, a data input to a second latch and to a firstlatch. The first latch is opened during a first phase of a clock cycleand the second latch is opened during a first phase of the clock cycle.Stage 318 includes providing, during a second operational mode, anoutput signal of the first latch to the second latch.

If method 300 includes stages 315-318 then stage 330 of detecting caninclude detecting a timing error during the first clock phase if a valuelatched in the second latch differs from the input data. Conveniently,stage 330 of detecting may include at least one of the following: (i)detecting during a high clock phase, (ii) immediately detecting a timingerror, (iii) performing a logical OR operations on multiple errorsignals provided from pairs of first and second latches.

Variations, modifications, and other implementations of what isdescribed herein will occur to those of ordinary skill in the artwithout departing from the spirit and the scope of the invention asclaimed. Accordingly, the invention is to be defined not by thepreceding illustrative description but instead by the spirit and scopeof the following claims.

1. A device having timing error management capabilities, the devicecomprises: a first input node adapted to receive input data; a firstlatch, a second latch and a comparator; a first multiplexer and a secondmultiplexer; wherein the second multiplexer is adapted to provide inputdata to the second latch from the first input mode during a firstoperational mode of the device and to provide a first latch outputsignal to the second latch during a second operational-mode; wherein thecomparator is adapted to compare, during a first clock phase, betweenthe first latch output signal and between a second latch output signaland in response to the comparison selectively generate an error signal.2. The device according to claim 1 further comprising a second inputnode adapted to receive input data during the second operational mode.3. The device according to claim 1 wherein the first latch is openduring high clock phases and wherein the second latch is open during lowclock phases.
 4. The device according to claim 1 wherein the comparatoris adapted to compare between second latch output signal representativeof input data during a second portion of previous clock cycle andbetween first latch output signal representative of input data during afirst portion of a current clock cycle.
 5. The device according to claim1 wherein the device is adapted to generate an error indicationimmediately upon an occurrence of a timing error.
 6. The deviceaccording to claim 1 further comprising a clock signal generator adaptedto delay a clock signal provided to the first and second latched inresponse to a timing error.
 7. The device according to claim 6 whereinthe delay period is about 10% of the clock cycle of the clock signal. 8.The device according to claim 1 further comprising a controller adaptedto determine at least one operational parameter in response to a load ofat least one component of the device and in response to at least onedetected timing error.
 9. The device according to claim 1 wherein thecomparator is adapted to compare, during at least a portion of the firstclock phase.
 10. The device according to claim 1 wherein the secondlatch is adapted to provide, during a first clock phase of a clock cycleoccurring after an error was detected, a second latch output signalrepresentative of the input signal the second latch received during thesecond phase of a clock cycle during which the error was detected.
 11. Amethod for timing error management, the method comprises: determining anoperational mode of a device; providing, during a first operationalmode, a data input to a second latch and to a first latch; wherein thefirst latch is opened during a second phase of a clock cycle and thesecond latch is opened during a first phase of the clock cycle;detecting a timing error during the first phase of the clock cycle if avalue latched in the second latch differs from the input data; andproviding, during a second operational mode, an output signal of thefirst latch to the second latch.
 12. The method according to claim 11further comprising determining operational parameters in response to atleast one error indications and load consumed by at least one componentof the device.
 13. The method according to claim 11 wherein detectingcomprises detecting during a high clock phase.
 14. The method accordingto claim 11 wherein the detecting comprises immediately detecting atiming error.
 15. The method according to claim 11 further comprisingdelaying the clock signal provided to the first latch and to the secondlatch in response to a reception of a timing error indication.
 16. Themethod according to claim 11 wherein the delaying comprises delaying byabout 10% of the clock cycle.
 17. The method according to claim 11wherein the detecting comprises performing a logical OR operations onmultiple error signals provided from pairs of first and second latched.18. The device according to claim 3 wherein the comparator is adapted tocompare between second latch output signal representative of input dataduring a second portion of previous clock cycle and between first latchoutput signal representative of input data during a first portion of acurrent clock cycle.
 19. The device according to claim 6 furthercomprising a controller adapted to determine at least one operationalparameter in response to a load of at least one component of the deviceand in response to at least one detected timing error.
 20. The methodaccording to claim 12 wherein detecting comprises detecting during ahigh clock phase.